M50FLW080BN5TG TR

M50FLW080A M50FLW080B 8-Mbit (13 x 64-Kbyte Blocks + 3 × 16 × 4 Kbyte Sectors) 3-V supply, Firmware Hub / low-pin-count Flash memory Feature summary ■ ■ ■ ■ ■ ■ Flash memory – Compatible with either the LPC interface or the FWH interface (Intel Spec rev1.1) used in PC BIOS applications – 5-signal communication interface supporting Read and Write operations – 5 additional general-purpose inputs for platform design flexibility – Synchronized with 33 MHz PCI clock PLCC32 (K) 16 blocks of 64 Kbytes – 13 blocks of 64 Kbytes each – 3 blocks, subdivided into 16 uniform sectors of 4 Kbytes each Two blocks at the top and one at the bottom (M50FLW080A) One block at the top and two at the bottom (M50FLW080B) Enhanced security – Hardware Write Protect pins for block protection – Register-based Read and Write Protection – Individual Lock Register for each 4 KByte sector Supply voltage – VCC = 3.0 to 3.6 V for Program, Erase and Read operations – VPP = 12 V for Fast Program and Erase Two interfaces – Auto Detection of Firmware Hub (FWH) or Low Pin Count (LPC) memory cycles for embedded operation with PC chipsets – Address/Address Multiplexed (A/A Mux) interface for programming equipment compatibility. Programming time: 10 µs typical October 2006 TSOP32 (NB) 8 × 14 mm TSOP40 (N) 10 × 20 mm ■ Program/Erase Controller – Embedded Program and Erase algorithms – Status Register bits ■ Program/Erase Suspend – Read other Blocks/Sectors during Program Suspend – Program other Blocks/Sectors during Erase Suspend ■ ELectronic signature – Manufacturer Code: 20h – Device Code (M50FLW080A): 80h – Device Code (M50FLW080B): 81h ■ Packages – ECOPACK® (RoHS compliant) Rev 4 1/64 www.st.com 1 Contents M50FLW080A, M50FLW080B Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 2.2 2.3 3 2.1.1 Input/Output communications (FWH0/LAD0-FWH3/LAD3) . . . . . . . . . . 13 2.1.2 Input communication frame (FWH4/LFRAME) . . . . . . . . . . . . . . . . . . . 13 2.1.3 Identification inputs (ID0-ID3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.4 General-purpose inputs (GPI0-GPI4) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.5 Interface configuration (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.6 Interface Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.7 CPU Reset (INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.8 Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.9 Top Block Lock (TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.10 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.11 Reserved for Future Use (RFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address/Address multiplexed (A/A Mux) signal descriptions . . . . . . . . . . 15 2.2.1 Address inputs (A0-A10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.2 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.4 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.5 Row/Column Address Select (RC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Supply signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 VPP optional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.3 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 2/64 Firmware Hub/low-pin-count (FWH/LPC) signal descriptions . . . . . . . . . 13 Firmware Hub/low-pin-count (FWH/LPC) bus operations . . . . . . . . . . . . 17 3.1.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.3 Bus Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.6 Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M50FLW080A, M50FLW080B 3.2 4 5 6 Contents Address/Address multiplexed (A/A Mux) bus operations . . . . . . . . . . . . . 19 3.2.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 Quadruple Byte Program command (A/A Mux interface) . . . . . . . . . . . . . 27 4.6 Double/Quadruple Byte Program command (FWH mode) . . . . . . . . . . . . 27 4.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9 Sector Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.11 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.12 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 Program/Erase Controller status (bit SR7) . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 Erase Suspend status (bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 Erase status (bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Program status (bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 VPP status (bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 Program Suspend status (bit SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 Block/Sector Protection status (bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.8 Reserved (bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Firmware Hub/low-pin-count (FWH/LPC) interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.1 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1.2 Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/64 Contents M50FLW080A, M50FLW080B 6.1.3 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Firmware Hub/low-pin-count (FWH/LPC) General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 Program and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Appendix A Block and sector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Appendix B Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 4/64 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 M50FLW080A, M50FLW080B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Signal names (FWH/LPC interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal names (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Addresses (M50FLW080A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Addresses (M50FLW080B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory identification input configuration (LPC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FWH Bus Read field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FWH Bus Write field definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LPC Bus Read field definitions (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LPC Bus Write field definitions (1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 A/A Mux bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Configuration Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Lock Register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 General-Purpose Input Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program and Erase times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FWH/LPC interface AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 A/A Mux interface AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 FWH/LPC interface clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FWH/LPC Interface AC signal timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A/A Mux interface Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A/A Mux interface Write AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 M50FLW080A block, sector and Lock Register addresses . . . . . . . . . . . . . . . . . . . . . . . . 52 M50FLW080B block, sector and Lock Register addresses . . . . . . . . . . . . . . . . . . . . . . . . 54 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5/64 List of figures M50FLW080A, M50FLW080B List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. 6/64 Logic diagram (FWH/LPC interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic diagram (A/A Mux interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PLCC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP32 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TSOP40 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FWH Bus Read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FWH Bus Write waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 LPC Bus Read waveforms (1-byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 LPC Bus Write waveforms (1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FWH/LPC interface AC measurement I/O waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 A/A Mux interface AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FWH/LPC interface clock waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FWH/LPC interface AC signal timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 A/A Mux interface Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A/A Mux interface Write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package outline . . . . . . . . . . 48 TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline . . . . . . . . . . . . 49 TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline . . . . . . . . . . . 50 Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Double/Quadruple Byte Program flowchart and pseudo code (FWH mode only). . . . . . . . 57 Quadruple Byte Program flowchart and pseudo code (A/A Mux interface only). . . . . . . . . 58 Program Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . 59 Chip Erase flowchart and pseudo code (A/A Mux interface only). . . . . . . . . . . . . . . . . . . . 60 Sector/Block Erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Erase Suspend and Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 62 M50FLW080A, M50FLW080B 1 Summary description Summary description The M50FLW080 is a 8 Mbit (1M x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing on production lines, an optional 12V power supply can be used to reduce the erasing and programming time. The memory is divided into 16 Uniform Blocks of 64 KBytes each, three of which are divided into 16 uniform sectors of 4 KBytes each (see Appendix A for details). All blocks and sectors can be erased independently. So, it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental program or erase commands from modifying their contents. Program and erase commands are written to the Command Interface of the memory. An onchip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set to control the memory is consistent with the JEDEC standards. Two different bus interfaces are supported by the memory: ● The primary interface, the FWH/LPC Interface, uses Intel’s proprietary Firmware Hub (FWH) and Low Pin Count (LPC) protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets. The M50FLW080 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. ● The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers, for production line programming prior to fitting the device in a PC Motherboard. In order to meet environmental requirements, ST offers the M50FLW080A and M50FLW080B in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. The memory is supplied with all the bits erased (set to ’1’). 7/64 Summary description Figure 1. M50FLW080A, M50FLW080B Logic diagram (FWH/LPC interface) VCC VPP 4 4 ID0-ID3 FWH0/LAD0 FWH3/LAD3 5 GPI0GPI4 FWH4/LFRAME WP M50FLW080A M50FLW080B TBL CLK IC RP INIT VSS AI09229B Table 1. 8/64 Signal names (FWH/LPC interface) FWH0/LAD0-FWH3/LAD3 Input/Output Communications FWH4/LFRAME Input Communication Frame ID0-ID3 Identification Inputs (ID0 and ID1 are Reserved for Future Use (RFU) in LPC mode) GPI0-GPI4 General Purpose Inputs IC Interface Configuration RP Interface Reset INIT CPU Reset CLK Clock TBL Top Block Lock WP Write Protect RFU Reserved for Future Use. Leave disconnected VCC Supply Voltage VPP Optional Supply Voltage for Fast Program and Erase Operations VSS Ground NC Not Connected Internally M50FLW080A, M50FLW080B Figure 2. Summary description Logic diagram (A/A Mux interface) VCC VPP 11 8 DQ0-DQ7 A0-A10 RC IC M50FLW080A M50FLW080B G W RP VSS AI09230B Table 2. Signal names (A/A Mux interface) IC Interface Configuration A0-A10 Address Inputs DQ0-DQ7 Data Inputs/Outputs G Output Enable W Write Enable RC Row/Column Address Select RP Interface Reset VCC Supply Voltage VPP Optional Supply Voltage for Fast Program and Erase Operations VSS Ground NC Not Connected Internally 9/64 Summary description PLCC connections A8 A9 RP VPP VCC RC A10 Figure 3. M50FLW080A, M50FLW080B A/A Mux GPI2 GPI3 RP VPP VCC CLK GPI4 A/A Mux 1 32 A7 A6 A5 A4 A3 A2 A1 A0 GPI1 GPI0 WP TBL ID3 ID2 ID1/RFU ID0/RFU M50FLW080A M50FLW080B 9 25 DQ0 FWH0/LAD0 IC (VIL) NC NC VSS VCC IC (VIH) NC NC VSS VCC INIT FWH4/LFRAME NC RFU G W NC DQ7 DQ1 FWH1/LAD1 DQ2 FWH2/LAD2 VSS VSS DQ3 FWH3/LAD3 DQ4 RFU DQ5 RFU DQ6 RFU 17 A/A Mux A/A Mux AI09231C 1. Pins 27 and 28 are not internally connected. Figure 4. TSOP32 connections A/A Mux NC NC NC VSS IC GPI4 CLK VCC VPP RP GPI3 GPI2 GPI1 GPI0 WP TBL 1 32 8 9 M50FLW080A 25 M50FLW080B 24 16 17 INIT FWH4/LFRAME NC RFU RFU RFU RFU G W NC DQ7 DQ6 DQ5 DQ4 FWH3/LAD3 VSS FWH2/LAD2 FWH1/LAD1 FWH0/LAD0 ID0/RFU ID1/RFU ID2 ID3 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A/A Mux NC NC NC NC IC (VIH) A10 RC VCC VPP RP A9 A8 A7 A6 A5 A4 AI09701B 10/64 M50FLW080A, M50FLW080B Figure 5. TSOP40 connections NC IC (VIL) NC NC NC NC GPI4 NC CLK VCC VPP RP NC NC GPI3 GPI2 GPI1 GPI0 WP TBL 1 40 10 M50FLW080A 31 11 M50FLW080B 30 20 21 VSS VCC FWH4/LFRAME INIT NC RFU RFU RFU RFU VCC VSS VSS FWH3/LAD3 FWH2/LAD2 FWH1/LAD1 FWH0/LAD0 ID0/RFU ID1/RFU ID2 ID3 VSS VCC W G NC DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 A/A Mux NC IC (VIH) NC NC NC NC A10 NC RC VCC VPP RP NC NC A9 A8 A7 A6 A5 A4 A/A Mux Summary description AI09232C Table 3. Addresses (M50FLW080A) Block Size (KByte) Address Range Sector Size (KByte) 64 F0000h-FFFFFh 16 x 4 KBytes 64 E0000h-EFFFFh 16 x 4 KBytes 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h-6FFFFh 64 50000h-5FFFFh 64 40000h-4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 64 00000h-0FFFFh 13 x 64 KBytes 16 x 4 KBytes 11/64 Summary description M50FLW080A, M50FLW080B Addresses (M50FLW080B)(1) Table 4. Block size (KByte) Address range Sector size (KByte) 64 F0000h-FFFFFh 16 x 4 KBytes 64 E0000h-EFFFFh 64 D0000h-DFFFFh 64 C0000h-CFFFFh 64 B0000h-BFFFFh 64 A0000h-AFFFFh 64 90000h-9FFFFh 64 80000h-8FFFFh 64 70000h-7FFFFh 64 60000h- 6FFFFh 64 50000h- 5FFFFh 64 40000h- 4FFFFh 64 30000h-3FFFFh 64 20000h-2FFFFh 64 10000h-1FFFFh 16 x 4 KBytes 64 00000h-0FFFFh 16 x 4 KBytes 13 x 64 KBytes 1. Also see Appendix A, Table 34 and Table 35 for a full listing of the Block Addresses. 12/64 M50FLW080A, M50FLW080B 2 Signal descriptions Signal descriptions There are two distinct bus interfaces available on this device. The active interface is selected before power-up, or during Reset, using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub/low-pin-count (FWH/LPC) signal descriptions section and the Address/Address multiplexed (A/A Mux) signal descriptions section, respectively, while the supply signals are discussed in the Supply signal descriptions section. 2.1 Firmware Hub/low-pin-count (FWH/LPC) signal descriptions Please see Figure 1 and Table 1. 2.1.1 Input/Output communications (FWH0/LAD0-FWH3/LAD3) All Input and Output Communications with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. 2.1.2 Input communication frame (FWH4/LFRAME) The Input Communication Frame (FWH4/LFRAME) signal indicates the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock, a new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is either proceeding or the bus is idle. 2.1.3 Identification inputs (ID0-ID3) Up to 16 memories can be addressed on a bus, in the Firmware Hub (FWH) mode. The Identification Inputs allow each device to be given a unique 4-bit address. A ‘0’ is signified on a pin by driving it Low, VIL, or leaving it floating (since there is an internal pull-down resistor, with a value of RIL). A ‘1’ is signified on a pin by driving it High, VIH (and there will be a leakage current of ILI2 through the pin). By convention, the boot memory must have address ‘0000’, and all additional memories are given addresses, allocated sequentially, from ‘0001’. In the Low Pin Count (LPC) mode, the identification Inputs (ID2-ID3) can address up to 4 memories on a bus. In the LPC mode, the ID0 and ID1 signals are Reserved for Future Use (RFU). The value on address A20-A21 is compared to the hardware strapping on the ID2ID3 lines to select the memory that is being addressed. For an address bit to be ‘1’, the corresponding ID pin can be left floating or driven Low, VIL (again, with the internal pulldown resistor, with a value of RIL). For an address bit to be ‘0’, the corresponding ID pin must be driven High, VIH (and there will be a leakage current of ILI2 through the pin, as specified in Table 24). For details, see Table 5. 13/64 Signal descriptions 2.1.4 M50FLW080A, M50FLW080B General-purpose inputs (GPI0-GPI4) The General Purpose Inputs can be used as digital inputs for the CPU to read, with their contents being available in the General Purpose Inputs Register. The pins must have stable data throughout the entire cycle that reads the General Purpose Input Register. These pins should be driven Low, VIL, or High, VIH, and must not be left floating. 2.1.5 Interface configuration (IC) The Interface Configuration input selects whether the FWH/LPC interface or the Address/Address Multiplexed (A/A Mux) Interface is used. The state of the Interface Configuration, IC, should not be changed during operation of the memory device, except for selecting the desired interface in the period before power-up or during a Reset. To select the FWH/LPC Interface, the Interface Configuration pin should be left to float or driven Low, VIL. To select the Address/Address Multiplexed (A/A Mux) Interface, the pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL; there will be a leakage current of ILI2 through each pin when pulled to VIH. 2.1.6 Interface Reset (RP) The Interface Reset (RP) input is used to reset the device. When Interface Reset (RP) is driven Low, VIL, the memory is in Reset mode (the outputs go to high impedance, and the current consumption is minimized). When RP is driven High, VIH, the device is in normal operation. After exiting Reset mode, the memory enters Read mode. 2.1.7 CPU Reset (INIT) The CPU Reset, INIT, signal is used to Reset the device when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. 2.1.8 Clock (CLK) The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0/LAD0-FWH3/LAD3. The Clock conforms to the PCI specification. 2.1.9 Top Block Lock (TBL) The Top Block Lock input is used to prevent the Top Block (Block 15) from being changed. When Top Block Lock, TBL, is driven Low, VIL, program and erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is driven High, VIH, the protection of the Block is determined by the Lock Registers. The state of Top Block Lock, TBL, does not affect the protection of the Main Blocks (Blocks 0 to 14). For details, see Appendix A. Top Block Lock, TBL, must be set prior to a program or erase operation being initiated, and must not be changed until the operation has completed, otherwise unpredictable results may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or Erase Suspend, and care should be taken to avoid this. 14/64 M50FLW080A, M50FLW080B 2.1.10 Signal descriptions Write Protect (WP) The Write Protect input is used to prevent the Main Blocks (Blocks 0 to 14) from being changed. When Write Protect, WP, is driven Low, VIL, Program and Erase operations in the Main Blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is driven High, VIH, the protection of the Block or Sector is determined by the Lock Registers. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 15). For details, see Appendix A. Write Protect, WP, must be set prior to a Program or Erase operation is initiated, and must not be changed until the operation has completed otherwise unpredictable results may occur. Similarly, unpredictable behavior is possible if WP is changed during Program or Erase Suspend, and care should be taken to avoid this. 2.1.11 Reserved for Future Use (RFU) Reserved for Future Use (RFU). These pins do not presently have assigned functions. They must be left disconnected, except for ID0 and ID1 (when in LPC mode) which can be left connected. The electrical characteristics for these signals are as described in the “Identification inputs (ID0-ID3)” section. 2.2 Address/Address multiplexed (A/A Mux) signal descriptions Please see Figure 2 and Table 2. 2.2.1 Address inputs (A0-A10) The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A19). They are latched during any bus operation by the Row/Column Address Select input, RC. 2.2.2 Data inputs/outputs (DQ0-DQ7) The Data Inputs/Outputs hold the data that is to be written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they carry the commands that are sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. 2.2.3 Output Enable (G) The Output Enable signal, G, controls the output buffers during a Bus Read operation. 2.2.4 Write Enable (W) The Write Enable signal, W, controls the Bus Write operation of the Command Interface. 2.2.5 Row/Column Address Select (RC) The Row/Column Address Select input selects whether the Address Inputs are to be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A19). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on its rising edge. 15/64 Signal descriptions 2.3 M50FLW080A, M50FLW080B Supply signal descriptions The Supply Signals are the same for both interfaces. 2.3.1 VCC supply voltage The VCC Supply Voltage supplies the power for all operations (read, program, erase, etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This is to prevent Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time, the operation aborts, and the memory contents that were being altered will be invalid. After VCC becomes valid, the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both VCC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. 2.3.2 VPP optional supply voltage The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program command description in A/A Mux interface and the Double/Quadruple Byte Program command description in FWH mode) and Fast Erase options of the memory. When VPP = VCC, program and erase operations take place as normal. When VPP = VPPH, Fast Program and Erase operations are used. Any other voltage input to VPP will result in undefined behavior, and should not be used. VPP should not be set to VPPH for more than 80 hours during the life of the memory. 2.3.3 VSS ground VSS is the reference for all the voltage measurements. Table 5. 16/64 Memory identification input configuration (LPC mode) Memory Number ID3 ID2 A21 A20 1 (Boot memory) VIL or float VIL or float 1 1 2 VIL or float VIH 1 0 3 VIH VIL or float 0 1 4 VIH VIH 0 0 M50FLW080A, M50FLW080B 3 Bus operations Bus operations The two interfaces, A/A Mux and FWH/LPC, support similar operations, but with different bus signals and timings. The Firmware Hub/Low Pin Count (FWH/LPC) Interface offers full functionality, while the Address/Address Multiplexed (A/A Mux) Interface is orientated for erase and program operations. See the sections below, The Firmware Hub/low-pin-count (FWH/LPC) bus operations and Address/Address multiplexed (A/A Mux) bus operations, for details of the bus operations on each interface. 3.1 Firmware Hub/low-pin-count (FWH/LPC) bus operations The M50FLW080 automatically identifies the type of FWH/LPC protocol from the first received nibble (START nibble) and decodes the data that it receives afterwards, according to the chosen FWH or LPC mode. The Firmware Hub/Low Pin Count (FWH/LPC) Interface consists of four data signals (FWH0/LAD0-FWH3/LAD3), one control line (FWH4/LFRAME) and a clock (CLK). Protection against accidental or malicious data corruption is achieved using two additional signals (TBL and WP). And two reset signals (RP and INIT) are available to put the memory into a known state. The data, control and clock signals are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds of up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. 3.1.1 Bus Read Bus Read operations are used to read from the memory cells, specific registers in the Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Read operation starts on the rising edge of the Clock signal when the Input Communication Frame, FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0FWH3/LAD3. On subsequent clock cycles the Host will send to the memory: ● ID Select, Address and other control bits on FWH0-FWH3 in FWH mode. ● Type+Dir Address and other control bits on LAD0-LAD3 in LPC mode. The device responds by outputting Sync data until the wait states have elapsed, followed by Data0-Data3 and Data4-Data7. See Table 6 and Table 8, and Figure 6 and Figure 8, for a description of the Field definitions for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of the signals. 17/64 Bus operations 3.1.2 M50FLW080A, M50FLW080B Bus Write Bus Write operations are used to write to the Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Write operation starts on the rising edge of the Clock signal when Input Communication Frame, FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-FWH3/LAD3. On subsequent Clock cycles the Host will send to the memory: ● ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3 in FWH mode. ● Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0LAD3. The device responds by outputting Sync data until the wait states have elapsed. See Table 7 and Table 9, and Figure 7 and Figure 9, for a description of the Field definitions for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of the signals. 3.1.3 Bus Abort The Bus Abort operation can be used to abort the current bus operation immediately. A Bus Abort occurs when FWH4/LFRAME is driven Low, VIL, during the bus operation. The device puts the Input/Output Communication pins, FWH0/LAD0-FWH3/LAD3, to high impedance. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received. A Bus Abort during the final TAR cycles is not guaranteed to abort the command. The bus, however, will be released immediately. 3.1.4 Standby When FWH4/LFRAME is High, VIH, the device is put into Standby mode, where FWH0/LAD0-FWH3/LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. 3.1.5 Reset During the Reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put to high-impedance. The device is in the Reset mode when Interface Reset, RP, or CPU Reset, INIT, is driven Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory reverts to the Read mode upon return from the Reset mode, and the Lock Registers return to their default states regardless of their states before Reset. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the affected memory cells no longer contain valid data. The device can take up to tPLRH to abort a Program or Erase operation. 3.1.6 Block Protection Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. 18/64 M50FLW080A, M50FLW080B 3.2 Bus operations Address/Address multiplexed (A/A Mux) bus operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional-style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH)/Low Pin Count (LPC) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected, all the blocks are unprotected. It is not possible to protect any blocks through this interface. 3.2.1 Bus Read Bus Read operations are used to read the contents of the Memory Array, the Electronic Signature or the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Write Enable (W) and Interface Reset (RP) must be High, VIH, and Output Enable, G, Low, VIL. The Data Inputs/Outputs will output the value, according to the timing constraints specified in Figure 16, and Table 28. 3.2.2 Bus Write Bus Write operations are used to write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH; and Write Enable, W, must be Low, VIL. The Data Inputs/Outputs are latched on the rising edge of Write Enable, W. See Figure 17, and Table 29, for details of the timing requirements. 3.2.3 Output Disable The data outputs are high-impedance when the Output Enable, G, is at VIH. 3.2.4 Reset During the Reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put at high-impedance. The device is in the Reset mode when RP is Low, VIL. RP must be held Low, VIL for tPLPH. If RP goes Low, VIL, during a Program or Erase operation, the operation is aborted, and the affected memory cells no longer contain valid data. The memory can take up to tPLRH to abort a Program or Erase operation. 19/64 Bus operations Table 6. M50FLW080A, M50FLW080B FWH Bus Read field definitions Clock Clock Cycle Cycle Number Count 1 1 2 1 3-9 7 Field START IDSEL ADDR FWH0- Memory FWH3 I/O 1101b XXXX XXXX Description I On the rising edge of CLK with FWH4 Low, the contents of FWH0FWH3 indicate the start of a FWH Read cycle. I Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. I A 28-bit address is transferred, with the most significant nibble first. For the multi-byte read operation, the least significant bits (MSIZE of them) are treated as Don't Care, and the read operation is started with each of these bits reset to 0. Address lines A20-21 and A23-27 are treated as Don’t Care during a normal memory array access, with A22=1, but are taken into account for a register access, with A22=0. (See Table 15) 10 1 MSIZE XXXX I This one clock cycle is driven by the host to determine the number of Bytes that will be transferred. M50FLW080 supports: single Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer (0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b). 11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. 13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 M=2n DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. If multi-Byte read operation is enabled, repeat cycle-16 and cycle-17 n times, where n = 2MSIZE. previous +1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. previous +1 1 TAR 1111b (float) N/A The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3. Figure 6. FWH Bus Read waveforms CLK FWH4 FWH0-FWH3 Number of clock cycles START IDSEL ADDR MSIZE TAR SYNC DATA TAR 1 1 7 1 2 3 M 2 AI08433B 20/64 M50FLW080A, M50FLW080B Table 7. Bus operations FWH Bus Write field definitions Clock Cycle Number Clock Cycle Count Field 1 1 START 2 1 FWH0- Memory FWH3 I/O 1110b IDSEL XXXX Description I On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle. I Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. 3-9 7 ADDR XXXX I A 28-bit address is transferred, with the most significant nibble first. Address lines A20-21 and A23-27 are treated as Don’t Care during a normal memory array access, with A22=1, but are taken into account for a register access, with A22=0. (See Table 15) 10 1 MSIZE XXXX I 0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b (Quadruple Byte Transfer). 11-18 M=2/4/8 DATA XXXX I Data transfer is two cycles, starting with the least significant nibble. (The first pair of nibbles is that at the address with A1A0 set to 00, the second pair with A1-A0 set to 01, the third pair with A1-A0 set to 10, and the fourth pair with A1-A0 set to 11. In Double Byte Program the first pair of nibbles is that at the address with A0 set to 0, the second pair with A0 set to 1) previous +1 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. previous +1 1 TAR 1111b (float) O The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. previous +1 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating it has received data or a command. previous +1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b, indicating a turnaround cycle. previous +1 1 TAR 1111b (float) N/A Figure 7. The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3. FWH Bus Write waveforms CLK FWH4 FWH0-FWH3 Number of clock cycles START IDSEL ADDR MSIZE DATA TAR SYNC TAR 1 1 7 1 M 2 1 2 AI08434B 21/64 Bus operations M50FLW080A, M50FLW080B Table 8. LPC Bus Read field definitions (1-byte) Clock Cycle Number Clock Cycle Count Field 1 1 START 2 1 LAD0- Memory LAD3 I/O 0000b CYCTYPE 0100b + DIR Description I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. I Indicates the type of cycle and selects 1-byte reading. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 0b for read. Bit 0 is Don’t Care. 3-10 8 ADDR XXXX I A 32-bit address is transferred, with the most significant nibble first. A23-A31 must be set to 1. A22=1 for memory access, and A22=0 for register access. Table 5 shows the appropriate values for A21-A20. 11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0-LAD3 during this cycle. 13-14 2 WSYNC 0101b O The LPC Flash Memory drives LAD0-LAD3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. 18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 19 1 TAR 1111b (float) N/A Figure 8. The LPC Flash Memory floats its outputs, the host takes control of LAD0-LAD3. LPC Bus Read waveforms (1-byte) CLK LFRAME LAD0-LAD3 START CYCTYPE + DIR ADDR TAR SYNC DATA TAR Number of clock cycles 1 1 8 2 3 2 2 AI04429 22/64 M50FLW080A, M50FLW080B Table 9. Bus operations LPC Bus Write field definitions (1 byte) Clock Clock Cycle Cycle Number Count Field LAD0LAD3 Memory I/O Description 1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents of LAD0-LAD3 must be 0000b to indicate the start of a LPC cycle. 2 1 CYCTYPE + DIR 011Xb I Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1 indicates the direction of transfer: 1b for write. Bit 0 is don’t care (X). 3-10 8 ADDR XXXX I A 32-bit address is transferred, with the most significant nibble first. A23-A31 must be set to 1. A22=1 for memory access, and A22=0 for register access. Table 5 shows the appropriate values for A21-A20. 11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant nibble. 13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a turnaround cycle. 14 1 TAR 1111b (float) O The LPC Flash Memory takes control of LAD0LAD3 during this cycle. 15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b, indicating it has received data or a command. 16 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b, indicating a turnaround cycle. 17 1 TAR 1111b (float) N/A The LPC Flash Memory floats its outputs and the host takes control of LAD0-LAD3. Figure 9. LPC Bus Write waveforms (1 byte) CLK LFRAME LAD0-LAD3 START CYCTYPE + DIR ADDR DATA TAR SYNC TAR Number of clock cycles 1 1 8 2 2 1 2 AI04430 23/64 Bus operations M50FLW080A, M50FLW080B Table 10. A/A Mux bus operations Operation G W RP VPP DQ7-DQ0 Bus Read VIL VIH VIH Don't Care Data Output Bus Write VIH VIL VIH VCC or VPPH Data Input Output Disable VIH VIH VIH Don't Care Hi-Z VIL or VIH VIL or VIH VIL Don't Care Hi-Z Reset 24/64 M50FLW080A, M50FLW080B 4 Command interface Command interface All Bus Write operations to the device are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings, and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface reverts to the Read mode when power is first applied, or when exiting from Reset. Command sequences must be followed exactly. Any invalid combination of commands will be ignored. See Table 11 for the available Command Codes. Table 11. Command codes Hexa-decimal Command 10h Alternative Program Setup, Double/Quadruple Byte Program Setup, Chip Erase Confirm 20h Block Erase Setup 32h Sector Erase Setup 40h Program, Double/Quadruple Byte Program Setup 50h Clear Status Register 70h Read Status Register 80h Chip Erase Setup 90h Read Electronic Signature B0h Program/Erase Suspend D0h Program/Erase Resume, Block Erase Confirm, Sector Erase Confirm FFh Read Memory Array The following commands are the basic commands used to read from, write to, and configure the device. The following text descriptions should be read in conjunction with Table 13. 4.1 Read Memory Array command The Read Memory Array command returns the device to its Read mode, where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the device to Read mode. Once the command is issued, the device remains in Read mode until another command is issued. From Read mode, Bus Read operations access the memory array. If the Program/Erase Controller is executing a Program or Erase operation, the device will not accept any Read Memory Array commands until the operation has completed. For a multibyte read, in the FWH mode, the address, that was transmitted with the command, will be automatically aligned, according to the MSIZE granularity. For example, if MSIZE=7, regardless of any values that are provided for A6-A0, the first output will be from the location for which A6-A0 are all ‘0’s. 25/64 Command interface 4.2 M50FLW080A, M50FLW080B Read Status Register command The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued, subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. 4.3 Read Electronic Signature command The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued, the Manufacturer Code and Device Code can be read using conventional Bus Read operations, and the addresses shown in Table 12. Table 12. Electronic Signature Codes Code Manufacturer Code Device Code M50FLW080A M50FLW080B Address(1) Data ...00000h 20h ...00001h 80h 81h 1. A22 should be ‘1’, and the ID lines and upper address bits should be set according to the rules illustrated in Table 5, Table 6 and Table 8. The device remains in this mode until another command is issued. That is, subsequent Bus Read operations continue to read the Manufacturer Code, or the Device Code, and not the Memory Array. 4.4 Program command The Program command can be used to program a value to one address in the memory array at a time. The Program command works by changing appropriate bits from ‘1’ to ‘0’. (It cannot change a bit from ‘0’ back to ‘1’. Attempting to do so will not modify the value of the bit. Only the Erase command can set bits back to ‘1’. and does so for all of the bits in the block.) Two Bus Write operations are required to issue the Program command. The second Bus Write cycle latches the address and data, and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the value in the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the address falls in a protected block, the Program operation will abort, the data in the memory array will not be changed, and the Status Register will indicate the error. During the Program operation, the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands are ignored. See Figure 21, for a suggested flowchart on using the Program command. Typical Program times are given in Table 18. 26/64 M50FLW080A, M50FLW080B 4.5 Command interface Quadruple Byte Program command (A/A Mux interface) The Quadruple Byte Program Command is used to program four adjacent Bytes in the memory array at a time. The four Bytes must differ only for addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH. Five Bus Write operations are required to issue the command. The second, third and fourth Bus Write cycles latch the respective addresses and data of the first, second and third Bytes in the Program/Erase Controller. The fifth Bus Write cycle latches the address and data of the fourth Byte and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the value in the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) During the Quadruple Byte Program operation, the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not modify its value. One of the erase commands must be used to set all of the bits in the block to ‘1’. See Figure 23, for a suggested flowchart on using the Quadruple Byte Program command. Typical Quadruple Byte Program times are given in Table 18. 4.6 Double/Quadruple Byte Program command (FWH mode) The Double/Quadruple Byte Program Command can be used to program two/four adjacent Bytes to the memory array at a time. The two Bytes must differ only for address A0; the four Bytes must differ only for addresses A0 and A1. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the start address and two/four data Bytes and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) During the Double/Quadruple Byte Program operation the memory will only accept the Read Status register and Program/Erase Suspend commands. All other commands are ignored. Note that the Double/Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not modify its value. One of the erase commands must be used to set all of the bits in the block to ‘1’. See Figure 22, for a suggested flowchart on using the Double/Quadruple Byte Program command. Typical Double/Quadruple Byte Program times are given in Table 18. 27/64 Command interface 4.7 M50FLW080A, M50FLW080B Chip Erase command The Chip Erase Command erases the entire memory array, setting all of the bits to ‘1’. All previous data in the memory array are lost. This command, though, is only available under the A/A Mux interface. Two Bus Write operations are required to issue the command, and to start the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) Erasing should not be attempted when VPP is not at VPPH, otherwise the result is uncertain. During the Chip Erase operation, the memory will only accept the Read Status Register command. All other commands are ignored. See Figure 25, for a suggested flowchart on using the Chip Erase command. Typical Chip Erase times are given in Table 18. 4.8 Block Erase command The Block Erase command is used to erase a block, setting all of the bits to ‘1’. All previous data in the block are lost. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the block address and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the block, or if at least one sector of the block (for the blocks that are split into sectors), is protected (FWH/LPC only) then the Block Erase operation will abort, the data in the block will not be changed, and the Status Register will indicate the error. During the Block Erase operation the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored. See Figure 26, for a suggested flowchart on using the Block Erase command. Typical Block Erase times are given in Table 18. 4.9 Sector Erase command The Sector Erase command is used to erase a Uniform 4-KByte Sector, setting all of the bits to ‘1’. All previous data in the sector are lost. Two Bus Write operations are required to issue the command. The second Bus Write cycle latches the Sector address and starts the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. (See the section on the Status Register for details on the definitions of the Status Register bits.) If the Sector is protected (FWH/LPC only), the Sector Erase operation will abort, the data in the Sector will not be changed, and the Status Register will indicate the error. During the Sector Erase operation the memory will only accept the Read Status Register and Program/Erase Suspend commands. All other commands are ignored. See Figure 26, for a suggested flowchart on using the Sector Erase Command. Typical Sector Erase times are given in Table 18. 28/64 M50FLW080A, M50FLW080B 4.10 Command interface Clear Status Register command The Clear Status Register command is used to reset Status Register bits SR1, SR3, SR4 and SR5 to ‘0’. One Bus Write is required to issue the command. Once the command is issued, the device returns to its previous mode, subsequent Bus Read operations continue to output the data from the same area, as before. Once set, these Status Register bits remain set. They do not automatically return to ‘0’, for example, when a new program or erase command is issued. If an error has occurred, it is essential that any error bits in the Status Register are cleared, by issuing the Clear Status Register command, before attempting a new program or erase command. 4.11 Program/Erase Suspend command The Program/Erase Suspend command is used to pause the Program/Erase Controller during a program or Sector/Block Erase operation. One Bus Write cycle is required to issue the command. Once the command has been issued, it is necessary to poll the Program/Erase Controller Status bit until the Program/Erase Controller has paused. No other commands are accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the device continues to output the contents of the Status Register until another command is issued. During the polling period, between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing, it is possible for the operation to complete. Once the Program/Erase Controller Status bit indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. During Program/Erase Suspend, the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Sector Erase or Block Erase then the program command will also be accepted. However, it should be noted that only the Sectors/Blocks not being erased may be read or programmed correctly. See Figure 24, and Figure 27, for suggested flowcharts on using the Program/Erase Suspend command. Typical times and delay durations are given in Table 18. 4.12 Program/Erase Resume command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the command. Once the command is issued, subsequent Bus Read operations read the contents of the Status Register. 29/64 Command interface Table 13. M50FLW080A, M50FLW080B Commands Command Cycle Bus operations(1) 1st 2nd Addr Data Addr Data 3rd Addr Data 4th Addr 5th Data Addr Data Read Memory Array(2),(3),(4) 1+ X FFh Read Addr Read Status Register(5),(3) 1+ X 70h X Read Electronic Signature(3) 1+ X 90h or Sig Signat (Sig (Signat (Sig (Signatu (Sig (Signat 98h Addr ure Addr) ure) Addr) re) Addr) ure) Program / Multiple Byte program (FWH)(6),(7),(4) 2 X 40h or Prog 10h Addr Quadruple Byte Program (A/A Mux)(6),(8) 5 X 30h A1 Prog Data1 Chip Erase(6) 2 X 80h X 10h (6) Read (Read (Read (Read (Read (Read (Read Data Addr2) Data2) Addr3) Data3) Addr4) Data4) Status Reg 2 X 20h BA D0h 2 X 32h SA D0h Clear Status Register(9) 1 X 50h Program/Erase suspend(10) 1 X B0h 1 X D0h 1 X 00h 1 X 01h 1 X 60h 1 X 2Fh 1 X C0h Sector Program/Erase Invalid resume(11) reserved(12) (Status Reg) (X) (Status Reg) (X) (Status Reg) Prog Data Erase(6) Block Erase (X) A2 Prog Data2 A3 Prog Data3 A4 Prog Data4 1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic Signature), the second and next cycles are READ. For the remaining commands, the second and next cycles are WRITE. BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC mode), and A21 and A20 are set according to the rules shown in Table 5 (for LPC mode) 2. After a Read Memory Array command, read the memory as normal until another command is issued. 3. “1+” indicates that there is one write cycle, followed by any number of read cycles. 4. Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation is all that is needed. 5. After a Read Status Register command, read the Status Register as normal until another command is issued. 6. After the erase and program commands read the Status Register until the command completes and another command is issued. 7. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t Care. PD is two or four Bytes depending on Msize code. 8. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1. 9. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’. 10. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase Suspend) and Program/Erase Resume commands can be issued. 11. The Program/Erase Resume command causes the Program/Erase suspended operation to resume. Read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. 12. Do not use Invalid or Reserved commands. 30/64 M50FLW080A, M50FLW080B 5 Status Register Status Register The Status Register provides information on the current or previous Program or Erase operation. The bits in the Status Register convey specific information about the progress of the operation. To read the Status Register, the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The text descriptions, below, should be read in conjunction with Table 14, where the meanings of the Status Register bits are summarized. 5.1 Program/Erase Controller status (bit SR7) This bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive. The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command is issued, until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is ‘1’. The end of a Program and Erase operation can be found by polling the Program/Erase Controller Status bit can be polled. The other bits in the Status Register should not be tested until the Program/Erase Controller has completed the operation (and the Program/Erase Controller Status bit is ‘1’). After the Program/Erase Controller has completed its operation, the Erase Status, Program Status, VPP Status and Block/Sector Protection Status bits should be tested for errors. 5.2 Erase Suspend status (bit SR6) This bit indicates that an Erase operation has been suspended, and that it is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). After a Program/Erase Suspend command is issued, the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is ‘0’, the Program/Erase Controller is active or has completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns to ‘0’. 31/64 Status Register 5.3 M50FLW080A, M50FLW080B Erase status (bit SR5) This bit indicates if a problem has occurred during the erasing of a Sector or Block. The Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Erase Status bit is ‘0’, the memory has successfully verified that the Sector/Block has been erased correctly. When the Erase Status bit is ‘1’, the Program/Erase Controller has applied the maximum number of pulses to the Sector/Block and still failed to verify that the Sector/Block has been erased correctly. Once the Erase Status bit is set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. 5.4 Program status (bit SR4) This bit indicates if a problem has occurred during the programming of a byte. The Program Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Program Status bit is ‘0’, the memory has successfully verified that the byte has been programmed correctly. When the Program Status bit is ‘1’, the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has been programmed correctly. Once the Program Status bit is set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. 5.5 VPP status (bit SR3) This bit indicates whether an invalid voltage was detected on the VPP pin at the beginning of a Program or Erase operation. The VPP pin is only sampled at the beginning of the operation. Indeterminate results can occur if VPP becomes invalid during a Program or Erase operation. Once the VPP Status bit set to ‘1’, it can only be reset to ‘0’ by a Clear Status Register command, or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. 32/64 M50FLW080A, M50FLW080B 5.6 Status Register Program Suspend status (bit SR2) This bit indicates that a Program operation has been suspended, and that it is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). After a Program/Erase Suspend command is issued, the memory may still complete the operation instead of entering the Suspend mode. When the Program Suspend Status bit is ‘0’, the Program/Erase Controller is active, or has completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued, the Program Suspend Status bit returns to ‘0’. 5.7 Block/Sector Protection status (bit SR1) The Block/Sector Protection Status bit can be used to identify if the Program or Erase operation has tried to modify the contents of a protected block or sector. When the Block/Sector Protection Status bit is reset to ‘0’, no Program or Erase operations have been attempted on protected blocks or sectors since the last Clear Status Register command or hardware reset. When the Block/Sector Protection Status bit is ‘1’, a Program or Erase operation has been attempted on a protected block or sector. Once it is set to ‘1’, the Block/Sector Protection Status bit can only be reset to ‘0’ by a Clear Status Register command or by a hardware reset. If it is set to ‘1’, it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to have failed, too. Using the A/A Mux Interface, the Block/Sector Protection Status bit is always ‘0’. 5.8 Reserved (bit SR0) Bit 0 of the Status Register is reserved. Its value should be masked. 33/64 Status Register Table 14. M50FLW080A, M50FLW080B Status Register bits Operation Program active Program suspended SR7 SR6 SR5 SR4 SR3 SR2 SR1 ‘0’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1 (1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ (1) X Program completed successfully ‘1’ X ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ Program failure due to Block/Sector Protection (FWH/LPC Interface only) ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase failure due to VPP Error ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ Erase failure due to Block/Sector Protection (FWH/LPC Interface only) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ Erase failure due to failed cell(s) in block or sector ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ 1. For Program operations during Erase Suspend, the SR6 bit is ‘1’, otherwise the SR6 bit is ‘0’. 34/64 M50FLW080A, M50FLW080B 6 Firmware Hub/low-pin-count (FWH/LPC) interface Configuration Firmware Hub/low-pin-count (FWH/LPC) interface Configuration Registers When the Firmware Hub Interface/Low Pin Count is selected, several additional registers can be accessed. These registers control the protection status of the Blocks/Sectors, read the General Purpose Input pins and identify the memory using the manufacturer code. See Table 15 for the memory map of the Configuration Registers. The Configuration registers are accessed directly without using any specific command code. A single Bus Write or Bus Read Operation, with the appropriate address (including A22=0), is all that is needed. 6.1 Lock Registers The Lock Registers control the protection status of the Blocks/Sectors. Each Block/Sector has its own Lock Register. Three bits within each Lock Register control the protection of each Block/Sector: the Write Lock Bit, the Read Lock Bit and the Lock Down Bit. The Lock Registers can be read and written. Care should be taken, though, when writing. Once the Lock Down Bit is set, ‘1’, further modifications to the Lock Register cannot be made until it is cleared again by a reset or power-up. See Table 16 for details on the bit definitions of the Lock Registers. 6.1.1 Write Lock The Write Lock Bit determines whether the contents of the Block/Sector can be modified (using the Program or Erase Command). When the Write Lock Bit is set, ‘1’, the Block/Sector is write protected – any operations that attempt to change the data in the Block/Sector will fail, and the Status Register will report the error. When the Write Lock Bit is reset, ‘0’, the Block/Sector is not write protected by the Lock Register, and may be modified, unless it is write protected by some other means. If the Top Block Lock signal, TBL, is Low, VIL, then the Top Block (Block 15) is write protected, and cannot be modified. Similarly, if the Write Protect signal, WP, is Low, VIL, then the Main Blocks (Blocks 0 to 14) are write protected, and cannot be modified. For details, see Appendix A and Table 16. After power-up, or reset, the Write Lock Bit is always set to ‘1’ (write-protected). 6.1.2 Read Lock The Read Lock bit determines whether the contents of the Block/Sector can be read (in Read mode). When the Read Lock Bit is set, ‘1’, the Block/Sector is read protected – any operation that attempts to read the contents of the Block/Sector will read 00h instead. When the Read Lock Bit is reset, ‘0’, read operations are allowed in the Block/Sector, and return the value of the data that had been programmed in the Block/Sector. After power-up, or reset, the Read Lock Bit is always reset to ‘0’ (not read-protected). 35/64 Firmware Hub/low-pin-count (FWH/LPC) interface Configuration Registers 6.1.3 M50FLW080A, Lock Down The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the Write Lock, Read Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required before changes to these bits can be made. When the Lock Down Bit is reset, ‘0’, the Write Lock, Read Lock and Lock Down Bits can be changed. Table 15. Configuration Register map Memory Address Default Value Access Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register FBC0100h N/A R Manufacturer Code Register FBC0000h 20h R Mnemonic Register Name Lock Registers (For details, see Appendix A) GPI_REG MANU_REG 1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to Table 9. Table 16. Bit Lock Register bit definitions Bit Name 7-3 2 1 0 Function(1) Value Reserved ‘1’ Bus Read operations in this Block or Sector always return 00h. ‘0’ Bus read operations in this Block or Sector return the Memory Array contents. (Default value). ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP or INIT) or after power-up. ‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). ‘1’ Program and Erase operations in this Block or Sector will set an error in the Status Register. The memory contents will not be changed. (Default value). ‘0’ Program and Erase operations in this Block or Sector are executed and will modify the Block or Sector contents. Read-Lock Lock-Down Write-Lock 1. Applies to the registers that are defined in Table 34 and Table 35. 36/64 M50FLW080A, M50FLW080B Table 17. Bit Firmware Hub/low-pin-count (FWH/LPC) interface Configuration General-Purpose Input Register definition Bit Name 7-5 4 3 2 1 0 Function(1) Value Reserved ‘1’ Input Pin GPI4 is at VIH ‘0’ Input Pin GPI4 is at VIL ‘1’ Input Pin GPI3 is at VIH ‘0’ Input Pin GPI3 is at VIL ‘1’ Input Pin GPI2 is at VIH ‘0’ Input Pin GPI2 is at VIL ‘1’ Input Pin GPI1 is at VIH ‘0’ Input Pin GPI1 is at VIL ‘1’ Input Pin GPI0 is at VIH ‘0’ Input Pin GPI0 is at VIL GPI4 GPI3 GPI2 GPI1 GPI0 1. Applies to the General Purpose Inputs Register (GPI-REG). 6.2 Firmware Hub/low-pin-count (FWH/LPC) General-Purpose Input Register The FWH/LPC General Purpose Input Register holds the state of the General Purpose Input pins, GPI0-GPI4. When this register is read, the state of these pins is returned. This register is read-only. Writing to it has no effect. The signals on the FWH/LPC Interface General Purpose Input pins should remain constant throughout the whole Bus Read cycle. 6.3 Manufacturer Code Register Reading the Manufacturer Code Register returns the value 20h, which is the Manufacturer Code for STMicroelectronics. This register is read-only. Writing to it has no effect. 37/64 Program and Erase times 7 M50FLW080A, M50FLW080B Program and Erase times The Program and Erase times are shown in Table 18. Table 18. Program and Erase times Parameter Interface Test Condition Byte Program Typ(1) Max Unit 10 200 µs Double Byte Program FWH VPP = 12V ± 5% 10(2) 200 µs Quadruple Byte Program A/A Multiplexed FWH VPP = 12V ± 5% 10(3) 200 µs VPP = 12V ± 5% 0.1(4) 5 VPP = VCC 0.4 5 VPP = 12V ± 5% 0.4 4 VPP = VCC 0.5 5 VPP = 12V ± 5% 0.75 8 VPP = VCC 1 10 VPP = 12V ± 5% 10 Block Program Sector Erase (4 KBytes)(5) Block Erase (64 KBytes) Chip Erase A/A Multiplexed s s s s Program/Erase Suspend to Program pause(5) 5 µs Program/Erase Suspend to Block Erase/Sector Erase pause(5) 30 µs 1. TA = 25°C, VCC = 3.3V 2. Time to program two Bytes. 3. Time to program four Bytes. 4. Time obtained executing the Quadruple Byte Program command. 5. Sampled only, not 100% tested. 38/64 Min M50FLW080A, M50FLW080B 8 Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 19. Absolute maximum ratings Symbol TSTG Parameter Storage Temperature Min. Max. Unit –65 150 °C VIO Input or Output range(1) –0.50 VCC + 0.6 V VCC Supply Voltage –0.50 4 V VPP Program Voltage –0.6 13 V VESD Electrostatic Discharge Voltage (Human Body model)(2) –2000 2000 V 1. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for less than 20ns during transitions. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) 39/64 DC and AC parameters 9 M50FLW080A, M50FLW080B DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 20, Table 21 and Table 22. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 20. Operating conditions Symbol VCC TA Table 21. Parameter Min. Max. Unit Supply Voltage 3.0 3.6 V Ambient Operating Temperature –20 85 °C FWH/LPC interface AC measurement conditions Parameter Value Unit 10 pF ≤1.4 ns 0.2 VCC and 0.6 VCC V 0.4 VCC V Value Unit Load Capacitance (CL) 30 pF Input Rise and Fall Times ≤10 ns 0 to 3 V 1.5 V Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Table 22. A/A Mux interface AC measurement conditions Parameter Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 10. FWH/LPC interface AC measurement I/O waveforms 0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform IO < ILO IO > ILO IO < ILO Output AC Tri-state Testing Waveform AI03404 40/64 M50FLW080A, M50FLW080B DC and AC parameters Figure 11. A/A Mux interface AC measurement I/O waveform 3V 1.5V 0V AI01417 Figure 12. AC measurement load circuit VDD VPP VDD 16.7kΩ DEVICE UNDER TEST CL 0.1µF 16.7kΩ 0.1µF CL includes JIG capacitance Table 23. AI08430 Impedance(1) Symbol Parameter Test Condition CIN(2) Input Capacitance VIN = 0V CCLK(2) Clock Capacitance VIN = 0V LPIN(3) Recommended Pin Inductance Min 3 Max Unit 13 pF 12 pF 20 nH 1. TA = 25°C, f = 1MHz. 2. Sampled only, not 100% tested. 3. See PCI Specification. 41/64 DC and AC parameters Table 24. Symbol M50FLW080A, M50FLW080B DC characteristics Parameter Min Max Unit FWH 0.5 VCC VCC + 0.5 V A/A Mux 0.7 VCC VCC + 0.3 V FWH/LPC –0.5 0.3 VCC V A/A Mux -0.5 0.8 V VIH(INIT) INIT Input High Voltage FWH/LPC 1.1 VCC + 0.5 V VIL(INIT) INIT Input Low Voltage –0.5 0.2 VCC V VIH Input High Voltage VIL Input Low Voltage Interface Test Condition FWH/LPC ILI(1) Input Leakage Current 0V ≤VIN ≤VCC ±10 µA ILI2 IC, IDx Input Leakage Current IC, ID0, ID1, ID2, ID3(2)= VCC 200 µA RIL IC, IDx Input Pull Low Resistor 100 kΩ VOH Output High Voltage VOL Output Low Voltage ILO Output Leakage Current VPP1 VPP Voltage VPPH VPP Voltage (Fast Erase) 20 FWH/LPC IOH = –500µA 0.9 VCC V A/A Mux IOH = –100µA VCC – 0.4 V FWH/LPC IOL = 1.5mA 0.1 VCC V A/A Mux IOL = 1.8mA 0.45 V 0V ≤VOUT ≤VCC ±10 µA 3 3.6 V 11.4 12.6 V 1.8 2.3 V VLKO(3) VCC Lockout Voltage ICC1 Supply Current (Standby) FWH/LPC FWH4/LFRAME = 0.9VCC, VPP = VCC All other inputs 0.9VCC to 0.1VCC VCC = 3.6V, f(CLK) = 33MHz 100 µA ICC2 Supply Current (Standby) FWH/LPC FWH4/LFRAME = 0.1 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6 V, f(CLK) = 33 MHz 10 mA ICC3 Supply Current (Any internal operation active) FWH/LPC VCC = VCC max, VPP = VCC f(CLK) = 33 MHz, IOUT = 0mA 60 mA ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA Supply Current (Program/Erase) A/A Mux Program/Erase Controller Active 20 mA VPP Supply Current (Read/Standby) VPP > VCC 400 µA VPP Supply Current (Program/Erase active) VPP = VCC 40 mA VPP = 12V ± 5% 15 mA ICC5(3) IPP IPP1(3) 1. Input leakage currents include High-Z output leakage for all bidirectional buffers with tri-state outputs. 2. ID0 and ID1 are RFU in LPC mode. 3. Sampled only, not 100% tested. 42/64 M50FLW080A, M50FLW080B DC and AC parameters Figure 13. FWH/LPC interface clock waveform tCYC tHIGH tLOW 0.6 VCC 0.5 VCC 0.4 VCC, p-to-p 0.4 VCC (minimum) 0.3 VCC 0.2 VCC AI03403 Table 25. Symbol FWH/LPC interface clock characteristics Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns Min 1 V/ns Max 4 V/ns CLK Slew Rate peak to peak 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. 43/64 DC and AC parameters M50FLW080A, M50FLW080B Figure 14. FWH/LPC interface AC signal timing waveforms CLK tCHQV tCHQZ tCHQX FWH0-FWH3/ LAD0-LAD3 tCHDX tDVCH VALID tFLCH tCHFH FWH4 VALID OUTPUT DATA START CYCLE FLOAT OUTPUT DATA VALID INPUT DATA AI09700 Table 26. FWH/LPC Interface AC signal timing characteristics Symbol PCI Symbol Parameter Value Unit tCHQV tval CLK to Data Out Min 2 ns Max 11 ns tCHQX(1) ton CLK to Active (Float to Active Delay) Min 2 ns tCHQZ toff CLK to Inactive (Active to Float Delay) Max 28 ns tAVCH tDVCH tsu Input Set-up Time(2) Min 7 ns tCHAX tCHDX th Input Hold Time(2) Min 0 ns tFLCH Input Set-up time on FWH4 Min 10 ns tCHFH Input Hold time on FWH4 Min 5 ns 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK and FWH4. 44/64 M50FLW080A, M50FLW080B DC and AC parameters Figure 15. Reset AC waveforms RP, INT tPLPH tPHWL, tPHGL, tPHFL W, G, FWH4/LFRAME Ai09705 Table 27. Reset AC characteristics Symbol Parameter tPLPH RP or INIT Reset Pulse Width RP or INIT Slew Rate(1) tPHFL RP or INIT High to FWH4/LFRAME Low tPHWL tPHGL RP High to Write Enable or Output Enable Low Test Condition Value Unit Min 100 ns Rising edge only Min 50 mV/ns FWH/LPC Interface only Min 30 µs A/A Mux Interface only Min 50 µs 1. See Chapter 4 of the PCI Specification. 45/64 DC and AC parameters M50FLW080A, M50FLW080B Figure 16. A/A Mux interface Read AC waveforms tAVAV ROW ADDR VALID A0-A10 NEXT ADDR VALID COLUMN ADDR VALID tAVCL tAVCH tCLAX tCHAX RC tCHQV G tGLQV tGHQZ tGLQX tGHQX DQ0-DQ7 VALID W tPHAV RP AI03406 Table 28. Symbol A/A Mux interface Read AC characteristics Parameter Test Condition Value Unit tAVAV Read Cycle Time Min 250 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC high Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tCHQV(1) RC High to Output Valid Max 150 ns tGLQV(1) Output Enable Low to Output Valid Max 50 ns tPHAV RP High to Row Address Valid Min 1 µs tGLQX Output Enable Low to Output Transition Min 0 ns tGHQZ Output Enable High to Output Hi-Z Max 50 ns tGHQX Output Hold from Output Enable High Min 0 ns 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV. 46/64 M50FLW080A, M50FLW080B DC and AC parameters Figure 17. A/A Mux interface Write AC waveforms Write erase or program setup A0-A10 Write erase confirm or valid address and data C1 R2 tCLAX tAVCH R1 tAVCL Automated erase or program delay Read Status Register Data Ready to write another command C2 tCHAX RC tWHWL tWLWH tCHWH W tVPHWH tWHGL G tQVVPL VPP tDVWH DIN1 DQ0-DQ7 tWHDX DIN2 VALID SRD AI04185 Table 29. Symbol A/A Mux interface Write AC characteristics Parameter Test Condition Value Unit tWLWH Write Enable Low to Write Enable High Min 100 ns tDVWH Data Valid to Write Enable High Min 50 ns tWHDX Write Enable High to Data Transition Min 5 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC High Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tWHWL Write Enable High to Write Enable Low Min 100 ns tCHWH RC High to Write Enable High Min 50 ns tVPHWH(1) VPP High to Write Enable High Min 100 ns tWHGL Write Enable High to Output Enable Low Min 30 ns tWHRL Write Enable High to RB Low Min 0 ns Output Valid, RB High to VPP Low Min 0 ns tQVVPL(1) (2) 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (VPP < 3.6V). 47/64 Package mechanical 10 M50FLW080A, M50FLW080B Package mechanical Figure 18. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package outline D D1 A1 A2 1 N B1 E2 e E1 E E3 F B 0.51 (.020) E2 1.14 (.045) A D3 R D2 CP D2 PLCC-A 1. Drawing is not to scale. Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, package mechanical data millimeters inches Symbol Typ Min Max A 3.18 A1 Min Max 3.56 0.125 0.140 1.53 2.41 0.060 0.095 A2 0.38 – 0.015 – B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 CP 0.10 0.032 0.004 D 12.32 12.57 0.485 0.495 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 – – – – E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 D3 7.62 0.300 E3 10.16 – – 0.400 – – e 1.27 – – 0.050 – – 0.00 0.13 0.000 0.005 – – – – F R N 48/64 Typ 0.89 32 0.035 32 M50FLW080A, M50FLW080B Package mechanical Figure 19. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package outline A2 N 1 e E B N/2 A D1 CP D DIE C A1 TSOP-a α L 1. Drawing is not to scale. Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 α 0° 5° 0° 5° B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 CP 0.100 0.0039 D 13.800 14.200 0.5433 0.5591 D1 12.300 12.500 0.4843 0.4921 – – – – E 7.900 8.100 0.3110 0.3189 L 0.500 0.700 0.0197 0.0276 N 32 e 0.500 0.0197 32 49/64 Package mechanical M50FLW080A, M50FLW080B Figure 20. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package outline 1 40 e D1 B 20 21 L1 E1 E A2 A 0.25 DIE A1 α L C CP TSOP40-M 1. Drawing is not to scale. Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, package mechanical data millimeters inches Symbol Typ Min A Typ Min 1.200 Max 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.100 0.210 0.0039 0.0083 C CP 0.100 0.0039 D1 10.000 9.900 10.100 0.3937 0.3898 0.3976 E 20.000 19.800 20.200 0.7874 0.7795 0.7953 E1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 – – 0.0197 – – 0.500 0.700 0.0197 0.0276 0° 5° L 50/64 Max L1 0.800 α 3° 0.0315 0° 5° 3° M50FLW080A, M50FLW080B 11 Part numbering Part numbering Table 33. Ordering information scheme Example: M50FLW080 A K 5 T G Device Type M50 = Flash Memory for PC BIOS Architecture FL = Firmware Hub/Low Pin Count Interface Operating Voltage W = VCC = 3.0 to 3.6V Device Function 080 = 8 Mbit (x8), Uniform Blocks and Sectors Array Matrix A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors Package K = PLCC32 NB = TSOP32: 8 x 14mm(1) N = TSOP40: 10 x 20mm(2) Device Grade 5 = Temperature range –20 to 85 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology P or G = ECOPACK® (RoHs compliant) 1. The TSOP32 package is only available in devices of the A type array matrix. 2. Devices delivered in this package are Not Recommended for New Design. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 51/64 Block and sector address table Appendix A Table 34. Block Size (KByte) Block and sector address table M50FLW080A block, sector and Lock Register addresses Sector Size (KByte) Sector No Register Address FF000h-FFFFFh 4 47 FBFF002 FE000h-FEFFFh 4 46 FBFE002 FD000h-FDFFFh 4 45 FBFD002 FC000h-FCFFFh 4 44 FBFC002 FB000h-FBFFFh 4 43 FBFB002 FA000h-FAFFFh 4 42 FBFA002 F9000h-F9FFFh 4 41 FBF9002 4 40 FBF8002 4 39 FBF7002 F6000h-F6FFFh 4 38 FBF6002 F5000h-F5FFFh 4 37 FBF5002 F4000h-F4FFFh 4 36 FBF4002 F3000h-F3FFFh 4 35 FBF3002 F2000h-F2FFFh 4 34 FBF2002 F1000h-F1FFFh 4 33 FBF1002 F0000h-F0FFFh 4 32 FBF0002 EF000h-EFFFFh 4 31 FBEF002 EE000h-EEFFFh 4 30 FBEE002 ED000h-EDFFFh 4 29 FBED002 EC000h-ECFFFh 4 28 FBEC002 EB000h-EBFFFh 4 27 FBEB002 EA000h-EAFFFh 4 26 FBEA002 E9000h-E9FFFh 4 25 FBE9002 4 24 FBE8002 4 23 FBE7002 E6000h-E6FFFh 4 22 FBE6002 E5000h-E5FFFh 4 21 FBE5002 E4000h-E4FFFh 4 20 FBE4002 E3000h-E3FFFh 4 19 FBE3002 E2000h-E2FFFh 4 18 FBE2002 E1000h-E1FFFh 4 17 FBE1002 E0000h-E0FFFh 4 16 FBE0002 Address Range F8000h-F8FFFh 64 F7000h-F7FFFh E8000h-E8FFFh 64 E7000h-E7FFFh 52/64 M50FLW080A, M50FLW080B Block No and Type 15 (Top) 14 (Main) M50FLW080A, M50FLW080B Table 34. Block and sector address table M50FLW080A block, sector and Lock Register addresses (continued) Block Size (KByte) Address Range Block No and Type Sector Size (KByte) 64 D0000h-DFFFFh 13 (Main) FBD0002 64 C0000h-CFFFFh 12 (Main) FBC0002 64 B0000h-BFFFFh 11 (Main) FBB0002 64 A0000h-AFFFFh 10 (Main) FBA0002 64 90000h-9FFFFh 9 (Main) FB90002 64 80000h-8FFFFh 8 (Main) FB80002 64 70000h-7FFFFh 7 (Main) FB70002 64 60000h-6FFFFh 6 (Main) FB60002 64 50000h-5FFFFh 5 (Main) FB50002 64 40000h-4FFFFh 4 (Main) FB40002 64 30000h-3FFFFh 3 (Main) FB30002 64 20000h-2FFFFh 2 (Main) FB20002 64 10000h-1FFFFh 1 (Main) FB10002 Sector No Register Address 0F000h-0FFFFh 4 15 FB0F002 0E000h-0EFFFh 4 14 FB0E002 0D000h-0DFFFh 4 13 FB0D002 0C000h-0CFFFh 4 12 FB0C002 0B000h-0BFFFh 4 11 FB0B002 0A000h-0AFFFh 4 10 FB0A002 09000h-09FFFh 4 9 FB09002 4 8 FB08002 4 7 FB07002 06000h-06FFFh 4 6 FB06002 05000h-05FFFh 4 5 FB05002 04000h-04FFFh 4 4 FB04002 03000h-03FFFh 4 3 FB03002 02000h-02FFFh 4 2 FB02002 01000h-01FFFh 4 1 FB01002 00000h-00FFFh 4 0 FB00002 08000h-08FFFh 64 07000h-07FFFh 0 (Main) 1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to Table 9. 53/64 Block and sector address table Table 35. Block Size (KByte) M50FLW080B block, sector and Lock Register addresses Sector Size (KByte) Sector No Register Address FF000h-FFFFFh 4 47 FBFF002 FE000h-FEFFFh 4 46 FBFE002 FD000h-FDFFFh 4 45 FBFD002 FC000h-FCFFFh 4 44 FBFC002 FB000h-FBFFFh 4 43 FBFB002 FA000h-FAFFFh 4 42 FBFA002 F9000h-F9FFFh 4 41 FBF9002 4 40 FBF8002 4 39 FBF7002 F6000h-F6FFFh 4 38 FBF6002 F5000h-F5FFFh 4 37 FBF5002 F4000h-F4FFFh 4 36 FBF4002 F3000h-F3FFFh 4 35 FBF3002 F2000h-F2FFFh 4 34 FBF2002 F1000h-F1FFFh 4 33 FBF1002 F0000h-F0FFFh 4 32 FBF0002 Address Range F8000h-F8FFFh 64 F7000h-F7FFFh 54/64 M50FLW080A, M50FLW080B Block No and Type 15 (Top) 64 E0000h-EFFFFh 14 (Main) FBE0002 64 D0000h-DFFFFh 13 (Main) FBD0002 64 C0000h-CFFFFh 12 (Main) FBC0002 64 B0000h-BFFFFh 11 (Main) FBB0002 64 A0000h-AFFFFh 10 (Main) FBA0002 64 90000h-9FFFFh 9 (Main) FB90002 64 80000h-8FFFFh 8 (Main) FB80002 64 70000h-7FFFFh 7 (Main) FB70002 64 60000h-6FFFFh 6 (Main) FB60002 64 50000h-5FFFFh 5 (Main) FB50002 64 40000h-4FFFFh 4 (Main) FB40002 64 30000h-3FFFFh 3 (Main) FB30002 64 20000h-2FFFFh 2 (Main) FB20002 M50FLW080A, M50FLW080B Table 35. Block Size (KByte) Block and sector address table M50FLW080B block, sector and Lock Register addresses (continued) Sector Size (KByte) Sector No Register Address 1F000h-1FFFFh 4 31 FB1F002 1E000h-1EFFFh 4 30 FB1E002 1D000h-1DFFFh 4 29 FB1D002 1C000h-1CFFFh 4 28 FB1C002 1B000h-1BFFFh 4 27 FB1B002 1A000h-1AFFFh 4 26 FB1A002 19000h-19FFFh 4 25 FB19002 4 24 FB18002 17000h-17FFFh 4 23 FB17002 16000h-16FFFh 4 22 FB16002 15000h-15FFFh 4 21 FB15002 14000h-14FFFh 4 20 FB14002 13000h-13FFFh 4 19 FB13002 12000h-12FFFh 4 18 FB12002 11000h-11FFFh 4 17 FB11002 10000h-10FFFh 4 16 FB10002 0F000h-0FFFFh 4 15 FB0F002 0E000h-0EFFFh 4 14 FB0E002 0D000h-0DFFFh 4 13 FB0D002 0C000h-0CFFFh 4 12 FB0C002 0B000h-0BFFFh 4 11 FB0B002 0A000h-0AFFFh 4 10 FB0A002 09000h-09FFFh 4 9 FB09002 4 8 FB08002 4 7 FB07002 06000h-06FFFh 4 6 FB06002 05000h-05FFFh 4 5 FB05002 04000h-04FFFh 4 4 FB04002 03000h-03FFFh 4 3 FB03002 02000h-02FFFh 4 2 FB02002 01000h-01FFFh 4 1 FB01002 00000h-00FFFh 4 0 FB00002 Address Range Block No and Type 18000h-18FFFh 64 1 (Main) 08000h-08FFFh 64 07000h-07FFFh 0 (Main) 1. In LPC mode, a most significant nibble, F, must be added to the memory address. For all registers, A22=0, and the remaining address bits should be set according to the rules shown in the ADDR field of Table 6 to Table 9. 55/64 Flowcharts and pseudo codes Appendix B M50FLW080A, M50FLW080B Flowcharts and pseudo codes Figure 21. Program flowchart and pseudo code Start Program command: – Write 40h or 10h – Write Address and Data (memory enters read status state after the Program command) Write 40h or 10h Write Address and Data NO Read Status Register Suspend SR7 = 1 NO YES do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – SR7 is set to 1 – Enter suspend program loop Suspend Loop YES SR3 = 0 NO VPP Invalid Error (1, 2) If SR3 = 1, – Enter the "VPP invalid" error handler NO Program Error (1, 2) If SR4 = 1, – Enter the "Program error" error handler YES SR4 = 0 YES FWH/LPC Interface Only SR1 = 0 NO Program to Protected Block/Sector Error (1, 2) If SR1 = 1, – Enter the "Program to protected block/sector" error handler YES End AI09092 1. A Status check of SR1 (Protected Block/Sector), SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 56/64 M50FLW080A, M50FLW080B Flowcharts and pseudo codes Figure 22. Double/Quadruple Byte Program flowchart and pseudo code (FWH mode only) Start Write 40h or 10h Write Start Address and 2/4 Data Bytes (3) Double/Quadruple Byte Program command: – write 40h or 10h – write Start Address and 2/4 Data Bytes (3) (memory enters read status state after the Double/Quadruple Byte Program command) NO Read Status Register Suspend SR7 = 1 NO YES do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – SR7 is set to 1 – Enter suspend program loop Suspend Loop YES SR3 = 0 NO VPP Invalid Error (1, 2) If SR3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If SR4 = 1, Program error: – error handler YES SR4 = 0 YES SR1 = 0 NO Program to Protected Block/Sector Error (1, 2) If SR1 = 1, Program to protected block/sector error: – error handler YES End AI09093 1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. A0 and/or A1 are treated as Don’t Care (A0 for Double Byte Program and A1-A0 for Quadruple Byte Program). For Double Byte Program: Starting at the Start Address, the first data Byte is programmed at the even address, and the second at the odd address. For Quadruple Byte Program: Starting at the Start Address, the first data Byte is programmed at the address that has A1-A0 at 00, the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that has A1-A0 at 11. 57/64 Flowcharts and pseudo codes M50FLW080A, M50FLW080B Figure 23. Quadruple Byte Program flowchart and pseudo code (A/A Mux interface only) Start Write 30h Write Address 1 & Data 1 (3) Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) Write Address 2 & Data 2 (3) (memory enters read status state after the Quadruple Byte Program command) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) NO Read Status Register Suspend SR7 = 1 NO YES do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – SR7 is set to 1 – Enter suspend program loop Suspend Loop YES SR3 = 0 NO VPP Invalid Error (1, 2) If SR3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If SR4 = 1, Program error: – error handler YES SR4 = 0 YES End AI09099 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1. 58/64 M50FLW080A, M50FLW080B Flowcharts and pseudo codes Figure 24. Program Suspend and Resume flowchart and pseudo code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register SR7 = 1 NO while SR7 = 0 YES SR2 = 1 NO Program Complete If SR2 = 0 Program completed YES Write a read Command Read data from another address Write D0h Write FFh Program Continues Read Data Program/Erase Resume command: – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI08426B 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. 59/64 Flowcharts and pseudo codes M50FLW080A, M50FLW080B Figure 25. Chip Erase flowchart and pseudo code (A/A Mux interface only) Start Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) Write 80h Write 10h do: – read Status Register Read Status Register SR7 = 1 NO while SR7 = 0 YES SR3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If SR3 = 1, VPP invalid error: – error handler YES SR4, SR5 = 0 If SR4, SR5 = 1, Command sequence error: – error handler YES SR5 = 0 NO Erase Error (1) If SR5 = 1, Erase error: – error handler YES End AI08428B 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 60/64 M50FLW080A, M50FLW080B Flowcharts and pseudo codes Figure 26. Sector/Block Erase flowchart and pseudo code Start Block/Sector Erase command: – Write 20h/32h – Write Block/Sector Address and D0h (memory enters read Status Register after the Block/Sector Erase command) Write 20h/32h Write Block/Sector Address and D0h NO Read Status Register Suspend SR7 = 1 NO YES do: – Read Status Register – If SR7=0 and a Program/Erase Suspend command has been executed – SR7 is set to 1 – Enter suspend program loop Suspend Loop YES SR3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If SR3 = 1, – Enter the "VPP invalid" error handler YES SR4, SR5 = 0 If SR4, SR5 = 1, – Enter the "Command sequence"error handler YES SR5 = 0 NO Erase Error (1) If SR5 = 1, – Enter the "Erase Error" error handler YES FWH/LPC Interface Only SR1 = 0 NO Erase to Protected Block/Sector Error (1) If SR1 = 1, – Enter the "Erase to protected Block/Sector" error handler YES End AI09094 1. If the Block Erase command is used on a block that is split into 4KByte sectors, each of the 16 sectors of the block should be unlocked before performing the erase operation. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 61/64 Flowcharts and pseudo codes M50FLW080A, M50FLW080B Figure 27. Erase Suspend and Resume flowchart and pseudo code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register SR7 = 1 NO while SR7 = 0 YES SR6 = 1 NO Erase Complete If SR6 = 0, Erase completed YES Read data from another block/sector or Program Write D0h Write FFh Erase Continues Read Data Program/Erase Resume command: – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI08429B 62/64 M50FLW080A, M50FLW080B 12 Revision history Revision history Table 36. Document revision history Date Version 02-Feb-2004 0.1 First Issue 21-Apr-2004 0.2 TSOP32 package added 24-May-2004 1.0 First public release 18-Aug-2004 2.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected 21-Jun-2005 3.0 Datasheet status changed to Full Datasheet. 26-Oct-2006 4 Changes Document converted to new ST template. Packages are ECOPACK® compliant. TLEAD removed from Table 19: Absolute maximum ratings. Blank option removed below Plating Technology in Table 33: Ordering information scheme. TSOP40 (N) package is Not Recommended for New Design. TSOP32 (NB) package only available in A type array matrix devices. TSOP40 package specifications updated (see Table 32 and Figure 20). 63/64 M50FLW080A, M50FLW080B Please Read Carefully: Information in this document is provided solely in connection with ST products. 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